Non-volatile semiconductor memory cells employing floating gates which are completely surrounded by an insulative layer such as silicon dioxide are well-known in the prior art. These cells are referred to as EPROMs, EEPROMs, flash EPROMs and flash EEPROMs. According to their basic operating principle, charge is transferred to a floating gate member (typically polysilicon) through a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc. In general, an EPROM or an EEPROM comprises a silicon substrate including source and drain regions which define a channel therebetween. The polysilicon floating gate is disposed above the channel and separated from the substrate by a relatively thin gate insulative layer. Likewise, the control gate is disposed above and insulated from the floating gate. An example of this category of device is shown in U.S. Pat. No. 3,500,142 and also in U.S. Pat. No. 4,203,158.
All non-volatile semiconductor memory cells store electrons (i.e., charge) on the floating gate in a capacitive manner. In the case of a flash EPROM or EEPROM cell, the entire memory array may be electrically erased at one time. That is, individual cells are not separately erasable as in current EEPROMs. This block erasable feature is described in co-pending application Ser. No. 07/253,775, filed Oct. 5, 1988 entitled "Low Voltage EEPROM Cell", assigned to the assignee of the present invention. U.S. Pat. No. 4,698,787 of Mukherjee et al., similarly discloses an electrically erasable programmable memory device which is programmed by hot-electron injection from the channel onto the floating gate, and erased by Fowler-Nordheim Tunnelling from the floating gate to the substrate.
The push toward higher density EPROM memory arrays has lead to the development of the contactless, electrically programmable and electrically erasable memory cell array. In the contactless array, cells employ elongated source/drain regions which are often referred to as "bit lines". These cells often require virtual ground circuitry for sensing and programming. An example of this type of array and a process for fabricating the same is disclosed in U.S. Pat. No. 4,780,424, which is assigned to the assignee of the present invention. A contactless cross-point cell whose floating gate is self-aligned to wordlines and bit lines within an array is also described in an article entitled, "A New Self-Aligned Field Oxide Cell For Multi-Mega Bit EPROMs", written by O. Bellezza et al., IEDM 1989, page 579-582.
According to the basic architecture of these arrays, the floating gates are formed over a thin gate oxide grown between the source and drain regions in the substrate. The source and drain regions form the bit lines of the array. Wordlines are generally defined perpendicular to the source and drain bit lines, with the array contacts being spaced-apart to serve multiple wordlines, e.g., 16, 32, 64, etc. An EPROM cell structure suitable for use in a virtual ground array architecture and which employs asymmetrically doped source and drain junctions is described in "An Asymmetrical Lightly-Doped Source (ALDS) Cell For Virtual Ground High Density EPROMs" by K. Yoshikawa et al., IEDM 1988, pages 432-435.
While the benefits of the contactless array architecture are obvious, there remains a need to improve features which affect the performance and manufacturability of these type of arrays. For example, the layout and/or process architecture of conventional contactless EPROM arrays is generally incompatible for tungsten wordline integration. Furthermore, many prior conventional EPROM processes incorporate non-self aligned source diffusions which constrict the minimum source diffusion width (e.g., due to bird's beak encroachment).
As will be seen, the present invention overcomes these drawbacks by providing a process for fabricating ultra-high density (e.g., 64 Mbit) contactless non-volatile semiconductor memory arrays useful in multimegabit EPROMs and flash EPROM applications. The architecture produced by the invented process is compatible for integration of tungsten metal wordlines. This scheme utilizes wordline trench-vias (patterned through the array planarization) filled either partially or completely by tungsten, or some alternative conductor.